This invention relates generally to semiconductor devices, their formation, structure and use, and specifically to methods of making transistor gates in nonvolatile memory integrated circuits.
Integrated circuits commonly include transistors. Many transistors have gates formed of a stack of materials that also form some wiring that connects the gates to other components. Examples of such arrangements are present in logic integrated circuits and in memory integrated circuits, including flash memory integrated circuits.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small form factor cards, which use an array of flash EEPROM cells. An example of a flash memory system is shown in FIG. 1, in which a memory cell array 1 is formed on a memory chip 12, along with various peripheral circuits such as column control circuits 2, row control circuits 3, data input/output circuits 6, etc.
One popular flash EEPROM architecture utilizes a NAND array, wherein a large number of strings of memory cells are connected through one or more select transistors between individual bit lines and a reference potential. A portion of such an array is shown in plan view in FIG. 2A. BL0-BL4 represent diffused bit line connections to global vertical metal bit lines (not shown). Although four floating gate memory cells are shown in each string, the individual strings typically include 16, 32 or more memory cell charge storage elements, such as floating gates, in a column. Control gate (word) lines labeled WL0-WL3 and string select lines DSL and SSL extend across multiple strings over rows of floating gates.
The top and bottom of the string connect to the bit line and a common source line respectively through select transistors (source select transistor and drain select transistor) as shown in FIG. 2B. Unlike memory cells, these transistors do not generally include floating gates. The gates of select transistors are electrically driven from the periphery through select lines that may extend over significant distances so that resistance of such lines is a concern. Transistors in peripheral circuits are also formed without floating gates and may also be controlled using lines that have significant resistance. Accordingly, there is a need for a transistor gate structure that can provide low resistance and for methods of forming such transistor gate structures in an efficient manner.